SY87700/701
Micrel
FUNCTIONAL DESCRIPTION
The evaluation board simplifies test and measurement of
the SY87700 and SY87701. This section covers the various
parts of the SY87700/701 evaluation board, and includes
detailed information about these blocks. Performance of
the SY87700/701 can be easily evaluated by following the
step-by-step instructions found in the “Test Configuration”
section.
Power Supply
The SY87700L and SY87701L are 3.3V devices.
Therefore, V CC should all be connected to 2.0V, and GND
connected to 0V, and V EE should be connected to –1.3V.
The SY87700V and SY87701V are 5.0V devices, therefore,
V CC should be connected to 2V, and GND to 0V, and V EE
should be connected to –3V.
Board Design and Layout
The evaluation board uses a force-sense design on the
signal inputs where the signal pins (source pins) on the
SY87700/701 are located on 50 ? line, on the last layer.
The sense lines, however, are located on layer 1. The force-
sense design is handy for monitoring inputs to the SY87700/
701 (such as input jitter). However, a 50 ? terminator needs
to be added to all unused sense outputs or the line will act
as a quarter wave stub notch filter.
LED
The SY87700/701 evaluation board features one LED
for monitoring the Link Fault Indicator (LFIN) pin. The LED
will turn on when the PLL has locked-on to the RDIN input
data stream, which indicates that LFIN has gone active
HIGH. Additionally, LFIN can only go active when CD is
HIGH and RDIN is within the 1000ppm frequency range of
the PLL.
Signal Inputs
Signal RDIN is 3.3V/5V PECL DC-coupled. Therefore,
the current level for DC-coupled applications is V CC –2V.
RDIN-DRIVEN
Evaluation Board
RDIN-BERT
If you are using a high frequency bit error rate tester
(such as the Agilent 70843B Error Performance Analyzer)
to drive RDIN ± , you will need to insert a 250ps Transition
Time Converter (TTC) to slow its edge down.
REFCLK
If you are using a high frequency clock or pulse generator
such as the Agilent 8133 to drive REFCLK, you will need to
insert a 2000ps Transition Time Converter (TTC) to slow its
edge down.
Signal Outputs
The SY87700/701 features PECL outputs for both
RDOUT ± and RCLK ± and TCLK ± . Unused pins should be
left FLOATING.
Test Configuration
This section contains step-by-step instructions for
configuring the SY87700 and SY87701 for clock and data
from the data stream of a BERT stack.
1. Set switches on evaluation board for desired data and
clock frequencies. There are seven switches in SW1:
1. FREQSEL1
2. FREQSEL2
3. FREQSEL3
4. CLKSEL
5. DIVSEL2
6. DIVSEL1
7. CD
See “ All Possible Legal Frequency and Divide Selec-
tions ” section on page 5, on how to set these switches. In
addition, CLKSEL should be set HIGH which configures
TCLK output as the recovered CLK from RDIN. If CLKSEL
is low, TCLK will be the synthesized clock output. Addition-
ally, CD should be set HIGH to allow the PLL to recover
RDIN. If CD is low, RDIN is forced low.
V CC
V CC
2. Connect GND to 0V.
3. Connect VCC to +2V.
Z=50 ?
Z=50 ?
R1
R2
R1
R2
J4
J5
RDIN+
RDIN –
GND 0V
V CC +2V
V EE
4. For 3.3V operation, connect VEE = – 1.3V.
For 5.0V operation, connect VEE = – 3.0V.
5. Connect REFCLK (TTL) inputs to reference clock.
Note: If using Agilent 8133A Pulse Generator, use
250ps Time Transistion Converters on the 8133
Note: For +5V systems
R1 = 82 ? , R2 = 130 ?
For +3V systems
R1 = 150 ? , R2 = 75 ?
V T = V CC – 2
( – 1.3V for 3.3V)
( – 3V for 5.0V)
outputs.
6. Connect TCLK (PECL) outputs to data inputs on test
equipment.
7. Connect RDINV (PECL) inputs to data source.
Figure 2. Test Set-Up
2
8. Connect RDOUT (PECL) to outputs on test equipment.
9. Connect RCLK outputs to clock inputs on test
equipment.
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